TbredB 1800+

[LL_NEO]

γιατί τέτοιος αφορισμός ρε συ jimk? Να σε διορθώσω και γω με τη σειρά μου και να σου πω οτι το pci ΔΕΝ είναι κλειδωμένο, γιατί πολύ απλά δεν έχει καμία σχέση με το fsb, για να μπορούσε να χρησιμοποιηθεί αυτή η έκφραση. Το nf2 έχει ξεχωριστό ρολόι που συγχρονίζει το pci bus στα 33ΜΗz. Βέβαια είτε pci lock είτε ξεχωριστό pci clock το πεις, γεγονός είναι οτι όλες οι καρτούλες και το ide δουλεύουν στα rated speeds, χωρίς προβλήματα.

[LL_NEO]

Και να το σχετικό άρθρο απο τον Aedan του www.aoaforums.com . Ξεσκονίστε τα αγγλικά σας και αρχίστε...

 

Lets really examine this nForce 2 board, the EPoX 8RDA+.

 

We know that the SPP (Northbridge) and MCP-T (Southbridge) are connected together via HyperTransport, rather than the more traditional PCI. If you look closely at the HyperTransport bus in the nForce 2 implementation, it operates at 800MB/sec. We also know that is a point-to-point bus, meaning that it only connects two devices together. It's also packetised, so instead of handling individual bytes, it handles packets of data, rather like most PC parts. (Hard disk, Ethernet, SCSI, floppy and so on). This is partly why the nForce can provide a feature called "StreamThrough". "StreamThrough" just means that the HyperTransport bus can guarantee dedicated bandwidth for particular data transfers. This means that the packets of data containing video information coming from the network connector will always be able to travel across the bus when they need to. They don't get pushed around by other devices such as the hard disks, or USB devices. Cool huh?

 

In addition, the memory can run asynchronously from the FSB. All this is important! Running things asynchronously means that each device run asynchronously needs it's own clock to keep it's own timing.

 

Before, when everything was running synchronously, there was a master clock that regulated everything. Each different frequency required was simply a division of the master clock. In one fell swoop, all this has changed!

 

The FSB and memory bus can run asynchonously, so each must have a separate clock. We also know that the AGP slot can run at a fixed clock - this is asynchronous, so it too needs it's own clock.

 

So far, we have 3 clocks, all independent of each other, and we haven't looked outside the SPP yet! Remember that HyperTransport bus? Well, that needs it's own clock too to regulate the transfers across it. In fact, for every 8 bits, HyperTransport needs a seperate clock. An 8bit wide HT bus needs one clock, a 16bit wide HT bus needs two clock, and a 32bit wide HT bus needs 4 clocks! nVidia's implementation only uses 8 bit wide transfers, so it only needs a single clock!

 

We're up at 4 clocks now, and none of them are generated from the same source.

 

Lets move down to the southbridge. This is where information gets a little more sketchy. We already know from the SPP that there's no master clock. Where does the SPP derive it's clocking from then? It would make little sense to derive it from the FSB, as the MCP-T doesn't connect to the FSB, nor is the MCP-T's connection to the SPP regulated by the FSB. It would make more sense to derive the MCP-T's clocking from the HyperTransport bus, as there is only one clock in this case. If the nForce2 chipset had a wider HyperTransport, then it would be more difficult, as there would be more clocks for the HyperTransport bus. An HT bus clock runs at 100MHz

 

Let's look at what needs a clock on the MCP-T. Hmm, this could be a nice place for a list...

 

 

 

 

 

Dual IDE interface (266) ?

 

PCI bridge (133) (33)

 

Audio Processing Unit (150) ?

 

Audio Codec Interface (1) ?

 

Ethernet (25) (20)

 

LPC Bus (Low Pin Count) - The remnants of the ISA bus. (1)

 

Dual USB (50) (20)

 

 

 

Remember, ALL of these are integrated onto the MCP-T. The first number in brackets illustrate the approximate bandwidth needed to run the various parts flat out. The second number illustrates the clock rate needed.

 

With each of these devices needing different speed clocks, it makes little sense to tie them all together into the non-existent clock generator. Remember that the SPP doesn't need the clock generator, as it has 4 separate clock generators in silicon just to handle it's own interfaces and keep things running asynchronously.

 

A lack of clock generator, and a radically different architecture to the standard Northbridge/Southbridge system calls for a lot of differences. This includes the MCP-T having it's own clock generator that runs independently of the SPP. Independence means that the audio, PCI, IDE and Ethernet all run in spec all the time. There's no question about PCI locks or an IDE lock, as that would require a complete redesign of the nForce2 chipset! Items like Ethernet and Audio are highly clockspeed sensitive. If you changed the clock for the Ethernet, your machine could no longer communicate with other devices on the network. The audio should be fairly obvious what would happen!

 

All in all, this points to all the peripherals running in spec regardless of what the FSB, Memory bus or AGP bus do.

 

As far as items like IDE disk corruption go, there's more to this than meets the eye. People are already beginning to trace some of this strange corruption through to memory, rather than hard disk. Why this should be is odd, but may be related to the caching all modern OSes use. Modern OSes rely heavily on data cached in main memory. This cache can be a sizable chunk of memory (On my 512MB W2K system, the cache is nearly 200MB in size!). Any slight corruption of the cache will cause nasty side effects as this corrupt data gets used. As this data usually includes the various control structures on the disk (FAT for FAT, MFT for NTFS, I-Nodes for EXT2FS and FNodes for HPFS), this can be very dangerous. Couple this with the fact that the control structures cached will be accessed EVERY time the OS wants to do something with the hard disk, and these become heavily used parts of memory.

 

Phew.. Hopefully that'll give a bit of a better idea about why the nForce2 architecture is so radiacally different from VIA and other's implementations. This means that things you used to understand may be totally different! Fortunately, as time goes on, people will understand the nForce2 better and better.

 

[BrwmogazoS]

JiMK edw den einai pctech forum... :shocked:

 

Eimaste mia pio stenh parea edw mesa...xwris na 8elw na katakrinw to Pctech forum...so chill out...

Gia overclocking kalo ksekina gia xtremesystems... :grin:

[crAss]

Ζηλεύω!!!!!!!!!!!!!!!!!!!!!!

Και μέχρι πριν λίγο καιρό ένιωθα μια χαρά με τον Palomino XP 1800+ @ 1850 (12.5*148). Και μάλιστα με σχετικά αθόρυβη αερόψυξη (η μεγαλύτερη ένταση θορύβου προέρχεται από τους 2*12εκ ανεμιστήρες του κουτιού...)

 

 

crAss

[@_zerocool]

JiMk

said:

kala re paidia.. signwmh alla den exete idea apo polla pragmata edw mesa......

 

μάλιστα και που το ξέρεις εσύ;