Verilog -Artiria-Eisodou

[Apanepai]

Kalispera,

thelw se Verilog na dimiourgisw mia artiria eisodou h opoia na exei 6 arithmous twn 8 duadikwn psifiwn.

 

Kanw tin anathesi ws eksis:

 

input [7:0] NUM [0:5];

 

Kai o compiler petaei to eksis sfalma:

 

near "[": expecting: ';'

 

Kai den einai problima stiksis opws arxika tha upothetame oloi.

 

Kamia idea? H kanenas allos tropos?

[system]

input [7:0] NUM [0:5]; ή input [7:0] NUM [5:0];

 

αλλιώς δώστα ένα ένα