pws briskw posa MHz einai i mnimi mou?

[ma05860-]

Sory re paidia gia tin ilithia erwtisi alla den borw na brw posa MHz einai i mnimi mou.Epsaksa tin mnimi alla den grafei pouthena ta MHz.Epsaksa sto bios alla kai pali tipota.Diabasa sto manual tou motherboard oti ypostirizei mnimi 100MHz,alla kai pali tipota gia tin mnimi.pou tha brw ayto pou zitaw???<BR>euxaristw prokatabolika.<IMG SRC="http://www.insomnia.gr/cpubb/smilies/cwm42.gif" border=0>

[GeoGR]

Antigrafw apo Sisoft Sandra Documentation <P>PC66/100 SDRAM Intel Specification - Version 1.0 to 1.2: <BR>PCx-abc-defm (e.g. PC100-322-622R) where: <BR>x - Speed rating (MHz). Memory bus speed should be equal/lower. <BR>a - CAS latency (CL cycles). Lower the better (faster), but more expensive. <BR>b - RAS to CAS delay (tRCD cycles). Lower the better. <BR>c - Row precharge (tRP cycles). Lower the better. <BR>d - Read data access time (tAC ns). Lower the better. <BR>e - SPD chip revision. 2 corresponds to SPD 1.2. <BR>f - Design revision. 2 corresponds to Rev 1.2. <BR>m - R for registered DIMMS. 256MB and bigger modules need to be registered. <P>PC66/100 SDRAM Extended Intel Specification - Version 1.2b+: <BR>PCx-abc-ddeefm (e.g. PC100-322-54122R) where: <BR>x - Speed rating (MHz). Memory bus speed should be equal/lower. <BR>a - CAS latency (CL cycles). Lower the better (faster), but more expensive. <BR>b - RAS to CAS delay (tRCD cycles). Lower the better. <BR>c - Row precharge (tRP cycles). Lower the better. <BR>dd - Read data access time (tAC ns). 54 corresponds to 5.4ns. Lower the better. <BR>ee - SPD chip revision. 12 corresponds to SPD 1.2. <BR>f - Design revision. The current is 2 corresponding to Rev 1.2. <BR>m - R for registered DIMMS. 256MB and bigger modules need to be registered. <P>PC133+ H/E/VC/SDRAM IBM/VIA/Micron/NEC Specification - Version 2.0: <BR>PCxm-abc-dde (e.g. PC133U-222-452, PC133R-333-542) <BR>x - Speed rating (MHz). Memory bus speed should be equal/lower. <BR>m - Module Type (R = Registered, U = Unbuffered). <BR>a - CAS latency (CL cycles). Lower the better (faster), but more expensive. <BR>b - RAS to CAS delay (tRCD cycles). Lower the better. <BR>c - Row precharge (tRP cycles). Lower the better. <BR>dd - Read data access time (tAC ns). 54 corresponds to 5.4ns. Lower the better. <BR>e - SPD chip revision. 2 corresponds to SPD 2.0. <P>PC1600+ DDR SDRAM Micron/Samsung/Hyundai Specification - Version 1.0: <BR>PCxm-aabc-dde (e.g. PC2100R-2533-750) <BR>x - Memory bandwidth (MB/s). Memory bus speed should be 1/16 of this or lower. <BR>m - Module Type (R = Registered, U = Unbuffered). <BR>aa - CAS latency (CL cycles). Lower the better (faster), but more expensive. <BR>b - RAS to CAS delay (tRCD cycles). Lower the better. <BR>c - Row precharge (tRP cycles). Lower the better. <BR>dd - Read data access time (tAC ns). 54 corresponds to 5.4ns. Lower the better. <BR>e - SPD chip revision. 0 corresponds to SPD 1.0. <P>RDRAM Rambus Specification - Version 1.0: <BR>xMB/a b c PCd (e.g. 256MB/16 ECC PC800) <BR>x - Module size in Mbytes on the module. <BR>a - Number of RDRAM devices on the module. <BR>b - Error correcting support (e.g. ECC) <BR>c - Reserved. <BR>d - Speed (Mega data transfers per second, Mt/s). Memory bus speed should be 1/2 of this or lower. <P><IMG SRC="http://www.insomnia.gr/cpubb/smilies/cwm1.gif" border=0> <P>Ta noumera pou anaferei tha ta vreis panw sti mnhmh sou<P>[This message has been edited by GeoGR (edited 23-02-2001).]<IMG SRC="http://www.insomnia.gr/cpubb/smilies/cwm16.gif" border=0> <p>[This message has been edited by GeoGR (edited 23-02-2001).]

[ma05860-]

euxaristw poli.tha koitaksw kai tha sou pw ti brika.