Denafrips Pontus II R2R premium DAC

Πωλείται Denafrips Pontus II R2R DAC (Black) σε άριστη κατάσταση και απόλυτα λειτουργικό (χρησιμοποιημένο ελάχιστα, στο κουτί του).

Χαρακτηριστικά

    ADAPTIVE FIFO BUFFER RECLOCKING

    The DENAFRIPS approach to address the jitters issue by FIFO BUFFER RECLOCKING. The adaptive FIFO buffer store the source digital audio data in the memory. These data are read from the memory using the low phase noise, precision FEMTO Clock, located right in the DAC.

    This technology is close to the perfection, especially so with the local FEMTO Clock. The jitter is so small that it can be neglected.

    PROPRIETARY, STATE-OF-THE-ART USB INTERFACE

    The PONTUS is equipped with the proprietary USB Audio Solution, powered by STM32F446 Advanced AMR Based MCU. DENAFRIPS redesigned and optimized circuitry, allow the DAC to be used as high-end DAC with computers / streamers. It supports 24bit/1536kHz PCM data stream, and native decoding of DSD up to DSD1024. It comes with licensed THESYCON USB Driver for Windows Platform.

    PROPRIETARY SPDIF DIGITAL AUDIO RECEIVER

    The SPDIF Coaxial, Optical, AES/EBU input support up to 24bit/192kHz digital audio format. The PONTUS abandon the use of Digital Audio Receiver chip. The digital data is decoded by the on-board FPGA (Field Programmable Gate Array), signal path is shortened and eliminated the undesirable coloration.

    PROPRIETARY R-2R AND DSD DECODING ARCHITECTURE

    The PONTUS is equipped with 24Bit R-2R DAC to decode PCM data stream and 32 steps FIR analogue filters hardware decoder to decode DSD data stream. These designs guaranteed the PCM format can be perfectly decoded, at the same time, the DSD format can be perfectly decoded as well. It is rare in the currently market that a R-2R DAC can hardware decode both the PCM and DSD formats.

    There is also a picture of the internal architecture with the following description:

    DIGITAL SIGNAL PROCESSING – All digital input data are stored in the on-board FPGA high-speed RAM.

    FEMTO CLOCK – These data are read from the memory using the low phase noise, accurate FEMTO Clock, located right in the DAC. The processed data are sent to the final stage Discrete R-2R, for DA conversion.

    R-2R LADDER NETWORK – The data bits are converted to analogue signal by the true balanced R-2R ladder network arrays. The linearity of the conversion is guaranteed by the high-precision thin film resistors, with low thermal effect temperature coefficient of the low 10/15ppm.